IR2110S

high and low side driver, SOP-16, high voltage, high speed, power MOSFET, IGBT driver, LSTTL output

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Price:: US $0.72~1.05 / piece [Get Latest Price]

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	US $0.72~1.05

PartNumber:: IR2110S

Brand:: International Rectifier - IR | Pack: SOP | D/C: 11+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
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Products Upload time: 2011-09-21

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Part Number:IR2110S
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Product Summary

The IR2110S is a high and low side driver. The IR2110S is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs of the IR2110S are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output driver of the IR2110S feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays of the IR2110S are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.

Parametrics

IR2110S absolute maximum ratings: (1)VS High side floating supply offset voltage: VB - 25 to VB + 0.3V; (2)VHO High side floating output voltage: VS - 0.3 VB to + 0.3V; (3)VCC Low side fixed supply voltage: -0.3 to 25V; (4)VLO Low side output voltage: -0.3 VCC to + 0.3V; (5)VDD Logic supply voltage: -0.3 VSS to + 25V; (6)VSS Logic supply offset voltage: VCC - 25 VCC to + 0.3V; (7)VIN Logic input voltage (HIN, LIN & SD): VSS - 0.3 VDD to + 0.3V; (8)TJ Junction temperature: 150℃; (9)TS Storage temperature: -55 to 150℃; (10)TL Lead temperature (soldering, 10 seconds): 300℃.

Features

IR2110S features: (1)Floating channel designed for bootstrap operation Fully operational to +500V or +600V Tolerant to negative transient voltage dV/dt immune; (2)Gate drive supply range from 10 to 20V; (3)Undervoltage lockout for both channels; (4)3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground V offset; (5)CMOS Schmitt-triggered inputs with pull-down; (6)Cycle by cycle edge-triggered shutdown logic; (7)Matched propagation delay for both channels; (8)Outputs in phase with inputs.